This is an individual Assignment

The attached Verilog file might help you with the implementation.

Submission:

Submit the project as a single file (doc or pdf) that contains:

1-      The code

2-      Description of the main parts of the code

3-      Screenshots of the simulation

4-      Explanation of the screenshots

5-      Additionally, submit the final code as text files.

Objectives:

1-       Design a Verilog HDL control sequence for a simple computer. The simple computer is a very small computer to give you practice in the ideas of designing a simple CPU with the Verilog HDL notation.

2-       To be familiar with the instruction cycle: fetch the instruction from memory, instruction decode, operand fetch and execution.

The simple computer has a two byte-addressable memory with size of 128byte. The memory is synchronous to the CPU, and the CPU can read or write a word in single clock period. The memory can only be accessed through the memory address register (MAR) and the memory buffer register (MBR).

To read from memory, you use: MBR <= Memory [MAR];

To write to memory, you use: Memory [MA] <= MBR;

The CPU has the following registers -- an accumulator (AC), a program counter (PC) and an instruction register (IR), an output register (OBR), a memory buffer register (MBR), a memory address register (MAR), and a general-purpose register (R0). There are also two output devices (OUTD0 and OUTD1) which can be used to display the results.

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