The execution cycles for various instructions are given in the following table. All units are pipelined. Loads and stores require the Integer ALU for address generations and the load/store unit for accessing memory.
computer science
Description
1.
[40] The execution cycles for various instructions are
given in the following table. All units are pipelined. Loads and stores require
the Integer ALU for address generations and the load/store unit for accessing memory.
 |
Simulate the execution of two loop iterations in the provide table. The execution is carried out on a two-issue dynamic-scheduling pipeline microarchitecture without/with speculations respectively. With speculation a reorder buffer (infinite size) is included to enforce in-order commit with up to 2 commits per cycle. A single CDB broadcasts/writebacks results after executions. Note that stores do not access memory until commit. Assume store will take 2 cycles at commit stage for memory storing.
Table 1 without speculation
|
Iter. |
Instruction |
Issue |
Execute |
Memory |
Write-CDB |
Comments |
|
|
1 |
L.D |
F0, 0(R1) |
1 |
2 |
3, 4 |
5 |
|
|
1 |
DIV.D |
F4, F2, F0 |
1 |
|
|
|
|
|
1 |
S.D |
F4, 0(R1) |
2 |
|
|
|
|
|
1 |
L |
R5, 0(R4) |
2 |
|
|
|
|
|
1 |
ADD |
R5, R5, R2 |
3 |
|
|
|
|
|
1 |
ST |
R5, 0(R4) |
3 |
|
|
|
|
|
1 |
SUBI |
R4, R4, #44 |
4 |
|
|
|
|
|
1 |
ADDI |
R1, R1, #8 |
4 |
|
|
|
|
|
1 |
BNE |
R1, R2, LOOP |
5 |
|
|
|
|
|
2 |
L.D |
F0, 0(R1) |
6 |
|
|
|
|
|
2 |
DIV.D |
F4, F2, F0 |
6 |
|
|
|
|
|
2 |
S.D |
F4, 0(R1) |
7 |
|
|
|
|
|
2 |
L |
R5,0(R4) |
7 |
|
|
|
|
|
2 |
ADD |
R5, R5, R2 |
8 |
|
|
|
|
|
2 |
ST |
R5, 0(R4) |
8 |
|
|
|
|
|
2 |
SUBI |
R4, R4, #44 |
9 |
|
|
|
|
|
2 |
ADDI |
R1, R1, #8 |
9 |
|
|
|
|
|
2 |
BNE |
R1, R2, LOOP |
10 |
|
|
|
|
|
Iter. |
Instruction |
Issue |
Execute |
Memory |
Write-CDB |
Commit |
Comments |
|
|
1 |
L.D |
F0, 0(R1) |
1 |
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