1- For the problems below document the design process. Clearly show the final compensator that you have obtained.




1- For the problems below document the design process. Clearly show the final compensator that you have obtained.
2-If you had to redesign (a compensator) briefly indicate what assumptions you had and the compensator you obtained (omit all other details in your final report).

3-If you were unable to a satisfactory design a compensator for a given problem after several trials, follow the step 2 however include your best results with more details as indicated by step 1.

4- Provide a nice / organized / clean report, including matlab script file of your work along with required figures (simulation, bode plots, etc.). Do not just print out Matlab command window, error messages, etc.



1-      For a unity feedback control system with plant transfer function of



Design phase-lag compensator such that the resulting controlled system has a Phase Margin of at least 45° and at most 65° with a static error constant coefficient in the range of 115 to 130.
Document the design process.

Verify your design by determining/showing the explicit form of the compensator, resulting Phase Margin, Gain Margin of the compensated system, as well as including step responses of the uncompensated system, gain adjusted system, and lag-compensated system.


2-      Design a phase-lead compensator for the system given in problem 1 (use the same values of Phase Margin and error coefficient).


3-      Compare and contrast the resulting compensated systems of problem 1 and 2. Is there any clear reason why one is a better choice than the other?


4-       Design a PID compensator for a unity feedback system with plant transfer function


Design a PID compensator that meets the following specifications:


a-  The closed-loop system transfer function has exactly two poles.

b-  The closed loop controlled system has dominant poles with

damped frequency of 4.5 rad/s and damping ratio greater than


c-  The closed-loop system exhibit zero steady state error due to a unit step input.

Clearly show the rational for the design, final compensator transfer function, and step response of closed-loop compensated system. 

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