Design an inverter to get NMH=NML and VM = VDD/2. Obtain the noise margins and the propagation delay time by simulating the layout and plotting dynamic and static characteristics.
engineering
Description
Design an inverter to get NMH=NML and VM = VDD/2. Obtain the noise margins and the propagation delay time by simulating the layout and plotting dynamic and static characteristics. (Load the inverter under test with an identical inverter before running the simulation.)
Then design an oscillator by placing 5 inverters designed above in a closed loop.
Run a simulation and plot the waveform at the output of each node. Compare the frequency of the generated signal with the expected frequency based upon the obtained tp of the inverter.
