Master the data flow modeling method of Verilog HDL language.

computer science


1. Experimental purpose 

◼ Learn the principles and design methods of Multiplexer; 

◼ Master the data flow modeling method of Verilog HDL language.

2. experimental content and principle 

◼ Design a 2-bit four-choice Multiplexer

3. Experimental requirements 

◼ Using a data flow description to implement a 2-bit fourselect data selector; 

◼ Pre-class tasks: programming, simulation, verification, to ensure logical correctness; 

◼ Laboratory tasks: 

◼ Configuration pin: Connect 4 inputs (4×2=8-bit signals) to 8 switches; connect output signal Y (2 bits) to 2 LEDs; 2-bit select signal S and 1 enable The signal can be connected to 3 buttons (pressed to 1 and released to 0). 

◼ Generate *.bit files and download them to the ARTIX7 teaching development board through the remote FPGA experimental platform. 

◼ Complete board level verification. ◼ Write an experiment report.

4. the experimental steps 

◼ Write a logical expression of Y[1] and Y[0]; 

◼ Use the data flow mode of the assign statement to program and simulate; 

◼ ARTIX7 teaching development board debugger: 

◼ Connect to the FPGA experiment platform; 

◼ download the local *.bit file to the FPGA on the ARTIX7 teaching development board; 

◼ press the button on the board to verify that the LED light display is consistent with the pressed or released state of the button. 

◼ experiment.

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