Description

 1. In the first part of the project you are to model a RAM and a simple memory controller in Verilog. The depth of the RAM is 256. Each dataline in RAM is 32 bits (4 bytes) and the memory controller reads and writes all 4 bytes at the same time. 

Your memory controller sits between the CPU and the RAM. It receives read and write requests from CPU, and does a complete handshake with it. Then it sends the read and write requests to the RAM. Once the data is read from or written to the RAM, it signals the completion of the operation along with data (in case of a memory read) with a READY signal to CPU.  

Note: rdEn and WrEn signals are active high, and are never asserted at the same time. The Addr is the address to read from or write to memory, and Data is the data to read from or write to memory. The Data port should have Z values whenever rdEn signal is deasserted. 

The memory controller has the following interface and Spec: