Description

The purpose of this assignment is modify a pipelined RISC CPU to improve it's forwarding unit. The stream site has the file “pipefwdcpu.lgf” on it, this is the 16 bit architecture described in the lectures. It has a 5 stage pipeline and a forwarding unit to handle 4 common cases:

ADD r0,r0,1 ADD r2,r0,r2 # r0 must be forwarded from the execute stage to the A input of the ALU in the next cycle

ADD r0,r0,1 ADD r2,r2,r0 # r0 must be forwarded from the execute stage to the B input of the ALU in the next cycle